cpu-architecture

cpu-architecture

Reasons of not achieving theoretical speedup time [on hold]

LRU Clock Replace Algorithm - What are reference bits initialized to?

Cache memory logic

Expanding opcodes

MMU ( memory management unit )and virtual memory

Address translation with multiple pagesize-specific TLBs

Virtually Indexed Caches

Is there any case where the Bimodal will be better than Not take?

For each of the following logical address, determine the physical address. Assume that page size is 1024 bytes

Is TLB used at all in the instruction fetching pipeline

Query regarding addressing modes

Query on various addressing modes?

How does a computer distinguish whether a binary pattern is an instruction or just a number?

What is the instruction format/length of an accumulator machine?

Instructions per second equation

Can Multiprocessor CPUs avoid context-switching?

Out-of-order execution vs. speculative execution

Indexed addressing mode and implied addressing mode

What control lines are asserted/set to 1 when a load double word instruction is called?

Why a 32-bit SoC has registers with size of 1 or 2 bytes?

CPU Redesign for Spectre and Meltdown

In context of computer architecture, what is the difference between control word and micro-instruction in case of micro programmed control unit?

Addressable memory of a CPU

Addressing a word inside memory frames

Cache coherence- MESI protocol

32-bit fixed instruction length in 64-bit memory space

What conditions might cause an integer subtraction or addition to overflow? I don't get the diffrence

What would be the consequences if the Memory Manager and the Processor Manager stopped communicating with each other?

What is the difference?

how cpu detect exceptions during execution?

PC VS MAR in Instruction Execution cycle

Basic SAP2 architecture code

What is the purpose of the reserved/undefined bit in the flag register?

Memory layout, does text segment have a max size?

Working out the maximum range of memory locations

Offset in cache Mips

What is the impact of locality principles on the pipelining techniques?

Computer Architecture - Splitting addresses for Direct, Associative and Set Associative Mapping

Are multiple clock domains common in modern processors?

maximum speed up achieved

Difference between instruction reference and data refernce

I have a query related to Computer Architecture

Calculating memory stalls while adding second level cache

What is the total amount of virtual memory covered by one entry of page tables at each level?

What is the difference between quadruple multiplexer and and the regular multiplexer?

what's the difference of strong ordered architecture and poorly ordered architecture

2 bit branch predictor with two for loops

Page table entry size - why a power of 2?

How does memory mapped I/O differentiate between Memory and I/O Transfer?

Average CPI of a processor

can we replace Link register with program counter?

Factors in designing Instruction set Arcitecture

Who place the data onto the cache?

How many bits for this op-code?

why an explicit single-cycle datapath is not needed?

Reorder Buffer commit

Decoding RISC-V immediate (UJ-TYPE)

Implement instructions to multicycle datapath

How does a disassembler work and how is it different from a decompiler?

Designing an Instruction Set with 2 Instructions

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